As shown in FIG. 1, for an ordinary liquid crystal display (LCD) panel having a low resolution (suppose the panel resolution is 1366×768), an input signal is sent to a timing control module (T-CON) 2 by an input signal connector 1 of a printed circuit board (PCB) 3, and the T-CON provides a distinguishable data signal to a source driver 4, and provides a timing control signal to the source driver 4 and a gate driver 5. For a high-level display device having a high resolution (the resolution of the display panel is 4K×2K or higher), because of a large number of data, a data transmission speed of the source driver and the T-CON is limited, usually more than twice the number of the source drivers, the gate drivers and the T-CONs (compared with the number of the source drivers, the gate drivers and the T-CONs shown in FIG. 1) are needed. When the number of the T-CONs is more than one, usually one field programmable gate array (FPGA) is needed to comprehensively arrange the data and control signals of a plurality of T-CONs. Suppose the LCD panel is divided into four areas to control the panel (as shown in FIG. 2A and FIG. 2B), four T-CONs are needed to control the data and the control signals of the four areas of the LCD panel (as shown in FIG. 3), respectively. When the LCD panel is controlled by a plurality of the areas, there is a certain delay in the data and control signals transmitted from different T-CONs to all of the areas of the LCD panel, which makes an asynchronous of display images of different areas and abnormal power-on display.